Today's Internet applications, such as web browsing, on-line shopping, and voice over IP (VOIP) are ubiquitous. The growing popularity of the Internet and new high bandwidth applications, such as video-on-demand (VOD), distance learning, video conferencing and medical/imaging are causing a dramatic increase in network traffic. Statistics show that average Internet traffic is doubling every three months. Meanwhile, an increasing number of applications require various levels of QoS, with guarantees of low latency and minimum bandwidth.
One way to handle the increasing demands is to increase the bandwidth capacity of switches. FIG. 1 shows a conventional switch in which incoming data packets 100 are processed according to their switch processing parameter (SPP) 102. The SPP may include a destination port number, priority, or other parameters within the data packet that is used by the switch to determine the appropriate switching process for the packet. The switch 104 must be able to perform global processing of all incoming data packets and route those data packets to the proper output port in accordance with the SPP of the data packet. As can be seen in FIG. 1, data packets with an SPP of “Y” are switched to output port 1 while data packets with an SPP of “X” are switched to output port K. However, as line rates increase, the interval time between the arrival of successive minimum-sized data packets at the input ports decreases, thereby decreasing the amounts of time available for global processing. Thus, the conventional switch has a fundamental scaling limitation as line rates increase because the line rate may increase to a level beyond the processing capability of the switch.
The mismatch that is developing between increasing line rates and switch processing capabilities has resulted in a bottleneck that occurs at switch nodes. Therefore, it is desirable to scale a switch so that it has higher bandwidth capacity. Two methods that are known in the art for scaling systems to higher capacities are multi-channel switching and bit slicing.
Under the multi-channel approach, multiple physical ports of a switch are grouped as a higher rate logical port. An example of such a switch is shown in FIG. 2. U.S. Pat. No. 5,838,679 issued to Kim et al. and U.S. Pat. No. 5,526,352 issued to Min et al., the entire disclosures of which are hereby incorporated by reference, disclose switches implementing the multi-channel switching approach. Multi-channel switching can provide high rate switching by exploiting the concept of channel grouping. As shown in FIG. 2, several input ports are grouped together as a channel, as are the output ports. Instead of being routed to a specific output port, data packets are routed to any output port belonging to an appropriate channel. With this configuration, several low rate ports can be grouped together and served as a high rate channel, thereby providing higher throughput. However, while multi-channel switching increases the bandwidth capacity for one logical channel, it does not increase the capacity of the system as a whole.
Under the bit slicing approach, each incoming data packet is divided into a number of subpackets. The subpackets are then passed in parallel through a switch fabric having a plurality of switch planes. U.S. Pat. No. 5,440,550 issued to Follett, the entire disclosure of which is hereby incorporated by reference, discloses a switch using bit slicing. FIG. 3(a) depicts an example of a switch using the bit slicing approach. FIG. 3(b) depicts a data packet before and after being sliced in the switch of FIG. 3(a). As the data packet 110 arrives at the input (point A2) of the slicing unit 106, the data packet will have the form as shown in FIG. 2(b). The slicing unit 106 will then slice the data packet evenly into N sub-packets, wherein N is the number of switch planes in the switch fabric. Each sub-packet maintains the same routing information or SPP of the data packet from which it was sliced, and each sub-packet contains 1/N of the original data packet from which it was sliced. The switch fabric is comprised of N identical switch planes 108 that are stacked together to provide a set of switches through which the sub-packets are processed in parallel. Each switch plane will process only 1/N of the original data packet rather than the full original data packet. After the sub-packets are processed by the switch fabric, they arrive in parallel at an assembler unit 116. The assembler unit then reconstructs the original data packet 110.
Because the number of switch ports is increased by a factor of N (there are N switch planes with K ports, as opposed to the switch of FIG. 1 which has only one switch plane with K ports) and because the line rate of each port remains constant, the stacked switch fabric used with bit slicing increases the overall system bandwidth capacity. However, because each successive sub-packet that reaches the switch will have a shorter length (only 1/N of the original data packet), the switch fabric must be able to process each sub-packet at N times the rate of processing in the single switch plane case. This property of bit slicing creates a problem when the switch is further scaled (larger and larger values for N), or when the line rate of the ingress ports is very high, because eventually a point is reached where the switch fabric does not have a sufficient amount of time to process a sub-packet before the next subpacket arrives. For the sub-packet, at each of the K ports of the switch plane, the switch plane must basically read the SPP, determine which output port is associated with that SPP, and route the sub-packets to the appropriate output port in accordance with the SPP in a non-blocking manner.
For example, when using bit slicing to scale an ATM switch from OC-48 (a line rate of approximately 2.488 Gb/s (gigabits per second)) to OC-192 (a line rate of approximately 10 Gb/s), the amount of time that the switch has to process each ATM cell decreases by a factor of four from 170 ns to 42.5 ns. With only 42.5 ns to process a subpacket, a switch running on a clock of 100 MHz must be able to perform global header processing every four clock cycles. Efficient implementations of switches having K input ports usually require K clock cycles to perform global header processing. So, for K=16 (as is common), 16 clock cycles are typically required. So when a switch has 42.5 ns to process a packet, the clock rate would need to be 400 MHz, which is very difficult to implement in a current VLSI design. Therefore, it is apparent that while bit slicing does result in a switch that can be scaled to a higher capacity, bit slicing suffers from a limitation in that the degree of scaling is limited by the speed at which the switch fabric can process SPPS.
It is therefore desirable to develop a switch that can be scaled to a high capacity without surpassing the switch fabric's ability to process incoming packets.